Este trabalho desenvolve a simulação do controle de velocidade de motor de indução com a técnica de controle direto de torque (Direct Torque Control - DTC), sendo executada em um dispositivo lógico programável tipo FPGA (Field Programable Gate Array). A simulação é realizada usando-se dois programas: O MATLAB/Simulink e o ModelSim, sendo que estes dois programas trabalham em modo de co-simulação provida pelo toolbox Link-for-ModelSim do Simulink. Enquanto a dinâmica do motor e do inversor é executada no MATLAB, o algoritmo de controle da estratégia DTC é executada no ModelSim. O algoritmo de acionamento DTC é escrito em linguagem de descrição de hardware VHDL (Very High Speed Integrated Circuit Hardware Description Language - VHSIC HDL) e utiliza a aritmética de ponto flutuante. Os resultados das simulações são apresentados e analisados no final deste trabalho.; This work presents a simulation of induction motor speed control using the technique of direct torque control (DTC), performed in a reprogrammable device type FPGA. The simulation is performed using two programs: MATLAB/Simulink and ModelSim, where these two programs work in a co-simulation mode, provide by Link for ModelSim toolbox from Simulink. While the motor and inverter dynamics is performed in MATLAB...

O trabalho faz um estudo dos sinais nervosos provenientes da medula espinhal. Determinar as características desses sinais é importante para entender seu mecanismo de ação e a forma de processá-los. O processamento destes sinais foi considerado para se obter o seu espectro no domínio frequência, haja vista as vantagens do uso deste em relação ao domínio do tempo. A transformada para os espectros de frequência deve ser realizada com uso de algoritmos rápidos que processem as amostras do sinal. A descrição de um algoritmo de Fast Fourier Transform em VHDL (Very High Speed Integrated Circuit Hardware Description Language) foi a primeira parte prática do trabalho. A validação deste hardware, sua síntese lógica e mapeamento para portas lógicas CMOS foram os passos seguintes. Neste trabalho foram aplicadas as células de portas lógicas MOS desenvolvidas com regras de 65nm no nível de layout pelo próprio autor e que foram caracterizadas no grupo de pesquisa para operação em tensões de alimentação ultra-baixas. A característica principal do trabalho foi que o hardware CMOS da Transformada Rápida foi sintetizado para operar com baixíssimo consumo de potência, pela operação da lógica em regime near-threshold...

In this paper is proposed and analyzed a digital hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier with almost unitary input power factor, composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The digital control allows a programmable THD (Total Harmonic Distortion) at the input currents, and it makes possible that the power rating of the switching-mode converters, connected in parallel, can be a small fraction of the total average output power, in order to obtain a compact converter, reduced input current THD and almost unitary input power factor. The proposed digital control, using a FPGA device and VHDL, offers an important flexibility for the associated control technique, in order to obtain a programmable PFC (Power Factor Correction) hybrid three-phase rectifier, in agreement with the international standards (IEC, and IEEE), which impose limits for the THD of the AC (Alternate Current) line input currents. Finally, the proposed control strategy is verified through experimental results from an implemented prototype. ©2008 IEEE.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES); Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP); Pós-graduação em Engenharia Elétrica - FEIS; Este trabalho trata da análise, desenvolvimento e implementação de um estágio Pré- Regulador Retificador Boost de alto fator de potência, para servir como fonte de alimentação para sistemas de iluminação fluorescente multi-lâmpadas, com potência de até 1.200 watts e com índices de qualidade tanto para a fonte de alimentação em corrente alternada quanto para o sistema de iluminação. Este conversor será controlado de forma digital, através da técnica dos valores médios instantâneos da corrente de entrada, desenvolvido através da linguagem de descrição de hardware VHDL (VHSIC HDL – Very High Speed Integrated Circuit Hardware Description Language) e implementado em um dispositivo FPGA (Field Programmable Gate Array) Spartan 3. Neste trabalho são apresentadas análises matemáticas, para a obtenção das funções de transferência pertinentes ao projeto dos compensadores, onde será aplicada uma metodologia de projeto capaz de projetar estes compensadores utilizando os diagramas de Bode, de módulo e de fase, e ainda contemplar as influencias dos dispositivos A/D...

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq); Pós-graduação em Engenharia Elétrica - FEIS; O objetivo deste trabalho é a concepção de uma lógica de controle digital com modulação por histerese variável usando um dispositivo programável FPGA (Field Programmable Gate Array) e linguagem de descrição de hardware VHDL (Hardware Description Language), aplicada em um retificador trifásico híbrido para a obtenção do Fator de Potência (FP) de entrada quase unitário. O Retificador Trifásico Híbrido (RTH) é uma estrutura composta por um retificador a diodos de 6 pulsos e por três retificadores monofásicos SEPIC conectados em paralelo. O controle digital proposto é capaz de impor a forma de onda das correntes de entrada, obtendose Distorção Harmônica Total (DHT) reduzida e fator de potência (FP) quase unitário, sendo que nesta condição, os retificadores monofásicos SEPIC conduzirão no máximo 33% da potência ativa total. Além disso, o uso de FPGAs dará ao Retificador Híbrido Trifásico uma flexibilidade adicional na operação, podendo substituir vários sistemas de múltiplos pulsos convencionais e reduzir custos para o sistema de controle por eliminar a confecção de circuitos complexos de controle analógico...

Em um passado recente os sistemas eram constituídos de partes discretas tais como microprocessadores, memórias e Application Specific Integrated Circuits (ASICs). Essa separação clara e simples tornava possível a especificação ser feita por uns poucos projetistas utilizando uma abordagem top-down: a partir de um modelo comportamental ou Register-Transfer Level (descritos em VHDL, por exemplo), progressivamente refinando o modelo ate o nível Transistor-to-Transistor. Entretanto, o avanço contínuo do processo de miniaturização de transistores possibilitou a criação de sistemas completos integrados em um único chip (também chamados de System-on-chip). Dado que esses sistemas s~ao tipicamente constituídos por diversos componentes complexos, um nível mais alto de abstração - o de sistema - foi criado, juntamente com suas linguagens associadas (como a linguagem SystemC), para facilitar o trabalho dos projetistas. As linguagens utilizadas para modelar no nível de sistema são diferentes das linguagens utilizadas para modelar nos níveis comportamental e Register-Transfer. Assim, surge o problema de como co-verificar componentes descritos em diferentes níveis de abstração; característica desejável para projetos de grande porte...

In this research work, was performed a study of main types of hardware modeling tools searching to verify the advantages of utilizing for modeling dynamic and concurrent systems and for its hardware implementation. It was observed that even though there are tools for this purpose, exists some points that may be worked out to facilitate access to this technology. So, was developed a method for facilitate implementation of systems modeled in Petri nets, in reconfigurable logic hardware. For that, was utilized a capture software where, from the graphic of the Petri net model, is generated a description in PNML (Petri Net Markup Language) format. From this description, is generated a hardware description file in VHDL (VHSIC Hardware Description Language) format, that may be loaded in a reconfigurable logic circuit. To make possible this stage, was performed the development of tool that generate a file in VHDL language from the description in PNML format. The developed tool is described in details, showing all stages and criteria utilized in the conversion. To validate the method, is showed an application example for this toll with the implementation in FPGA (Field Programmable Gate Arrow), of a Petri net modeling a hypothetic industrial plant. Finally...

There are machines that need large processing speed for its correct working, these machines have a critical time response processing. When it is considered that aspect coupled with the need for control of static and dynamic behavior of a system arrives at the controller with strong demands on runtime. This dissertation compares discrete controllers implemented in fixed point with different accuracies, using for both the simulation of the behavior of controllers manufactured in Matlab command language and VHDL 2008. VHDL 2008 still in development and standardization by the IEEE. The VHDL language is used in FPGAs that are high speed devices with parallel processing capability. The main objective of this work is the study and implementation of discrete controllers in FPGA with the help of the VHDL 2008 language, determining its strengths and limitations, particularly in regard to the structure of programming, error analysis and demand for resources. Results show that accuracy still need some improvements a standard to the VHDL 4.0, known as VHDL 2008, is delivered to the market a stable standard. However, knowing it limitations, it is possible implementations and use in conversion of analog signals to discrete, such as control and dynamic systems simulation like servomechanisms.; Existem máquinas que necessitam de uma grande velocidade de processamento para seu correto trabalho...

Este proyecto consiste en el estudio de un sistema de visión estéreo controlador por Hardware. El hardware que controlará el sistema será una FPGA de la marca Digilent, con un chip Xilinx Spartan-6 LX45. La cámara estéreo, también de Digilent, estará compuesta por dos sensores que captaran dos imágenes a la vez, desplazadas entre sí lateralmente. La cámara estero captara imágenes que será almacenadas y tratadas por la FPGA, para posteriormente enviarlas a través de un puerto HDMI hacia una pantalla. Para el diseño de todo el sistema se utilizará el lenguaje de descripción hardware VHDL (Very High Description Language). Para el estudio se partirá de un diseño básico desarrollado por el fabricante. Un vez estudiado y entendido el sistema, se procederá al desarrollo de diseños relacionados con la visión estéreo y que utilicen nuestro sistema, como son el cálculo de mapas de disparidad y la generación de anáglifos. _________________________________________________________________________________________________________________; This Project consist in the study of a stereo vision system controller by hardware. The hardware, that will handle the system, will be a FPGA of Digilent, with a chip Xilinx Spartan-6 LX45. The stero cam...

En este trabajo se presenta un estudio de la implementación hardware del cálculo de los cumulantes de segundo y cuarto orden, para ser empleados en la extracción de características dentro de un proceso completo de selección, y extracción de características para la clasificación de señales procedentes de electrocardiogramas (ECG). Estos cumulantes son los que se derivan de estudios como el de [Gua 12], que implementa un sistema completo de selección y clasificación de características en sistemas embebidos. Para la realización de este estudio se emplean datos reales procedentes de una de las mayores bases de datos que proporcionan señales procedentes de electrocardiogramas (MIT/BIH Arrythmia). A partir de estas señales se llega a la obtención de las características más significativas de cada uno de los datos reduciendo el volumen de información a través del cálculo de los cumulantes de segundo y cuarto orden. Con este estudio lo que se pretende es comprobar si es posible una aceleración a través de la implementación Hardware del cálculo de estos dos cumulantes ya mencionados. Finalmente se presentarán los resultados obtenidos de la aceleración que se ha conseguido gracias al diseño propuesto a través de VHDL (Hardware Description Language)...

Este trabalho apresenta um sistema de Síntese de Alto Nível — geração automática de uma descrição estrutural no nível RT a partir de uma descrição comportamental algorítmica [MCF 88] —, abordando as tarefas de compilação para representação interna, transformações comportamentais, escalonamento, alocação, mapeamento e gera.são do controle. Sua principal contribuição esta na fase de transformações comportamentais, através da qual é possível explorar globalmente o paralelismo existente na descried° do sistema digital e, de maneira sistemática, pesquisar o espaço de projeto, ou seja, as possíveis implementações para o sistema digital, identificando a que melhor satisfaz as restrições especificadas pelo projetista. A Linguagem de Descried° de Hardware (HDL) usada no sistema de síntese é VHDL que oferece recursos para se descrever comportamento e estrutura, e se especificar restrições de projeto, alem de ter sido adotada como padrão pela IEEE. Parte-se da descried° algorítmica em VHDL comportamental do sistema digital. Tal descrição é compilada para uma representação interna baseada em grafos: cada bloco básico — seqüência de operações sem desvio — e representado por um Grafo de Fluxo de Dados (GFD); a transferência de controle entre blocos básicos — desvios condicionais e incondicionais — é representada pelo Grafo de Fluxo de Controle (GFC); e as relações de hierarquia — entidade...

Following the simple observation that the interconnection of a set of quantum optical input-output devices can be specified using structural mode VHSIC Hardware Description Language (VHDL), we demonstrate a computer-aided schematic capture workflow for modeling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.; Comment: 20 pages, 6 figures, 1 table, 6 code listings

Hardware Description Languages are used as the connecting links between the design of a digital system and the way this design is being represented in computers, with the ultimate goal being the simulation and verification of that design before the construction of any prototype. In this thesis, we follow all the steps of a RISC architecture design and finally use VHDL as the tool to describe, simulate and verify the design. By the unique abilities of VHDL we give both a structural and a behavioral description where the latter contains multiple description levels, from gate to Processor-Memory-Switch (PMS) . The final step is the simulation to verify the proper operation of the design or to assist in pinpointing design errors for correction .

Very high speed integrated circuit Hardware Description Language (VHDL) is utilized in this project to model a Morphological Image Processor (MIP) Array. Both behavioral and structural models have been established at the system level, and the simulation results from both models are consistent with each other. The successful implementation of the models accomplishes our original goal to document the MIP with VHDL. It is observed from the project that VHDL is a powerful language. It is flexible since it can be used to model any level of a system independent of the technology.

The goal of this thesis is to demonstrate the feasibility of converting a synchronous general purpose microprocessor design into one using an asynchronous methodology. This thesis is one of three parts that details the entire design of an asynchronous version of the MIPS R3000 microprocessor. The design includes the main architectural features of the R3000: the 5-stage pipeline, the thirty-two 32-bit register bank, and the 32-bit address and data paths. To limit the size of the project, the memory and coprocessor are excluded. Therefore, this design has implemented the entire set of instructions from the original synchronous version with the exception of the coprocessor support instructions. The three participants in this project are Paul Fanelli, Kevin Johnson, and Scott Siers. Paul Fanelli developed the Very High Speed Integrated Circuit Hardware Description Language (VHDL) models for the processor. Three models, behavioral, dataflow, and structural, were constructed. Kevin Johnson designed the register bank, the arithmetic logic unit, and the shifter, including schematic diagrams and layouts. Scott Siers designed the pipeline stages, the multiplier/divider, the exception handler, and the completion signal generator, including schematic diagrams and layout. Each of the participants has written a separate thesis that covers one part of the total design.

The design and implementation of a key-generation algorithm will be discussed. The steps in the procedure consist of choosing a baseline algorithm for comparison, designing a new algorithm, testing and comparing the algorithms using C language programs, and then implementing the new algorithm using VHDL. The final result of testing the algorithm implemented in VHDL will be compared to the original results obtained from the C program implementing the new algorithm. C language programs of the chosen algorithms will be developed to verify their similarity and functionality. The results will be used to decide if the new algorithm selected for implementation is sufficiently robust, and similar in functionality to the baseline algorithm. After the algorithm is selected, it will be implemented in a hardware description language. This will be done for purposes of demonstrating top down design and hardware efficiency. This process will involve the steps of moving the design from an abstract algorithmic view, to a high level (behavioral) hardware description, and then to a low level (structural) description. This process will illustrate the details of moving the design from a theoretical level to a practical implementation level.

Optical character recognition is useful in many aspects of business. However, the use of conventional computers to provide a solution to this problem has not been very effective. Over the past two decades, researchers have utilized artificial neural networks for optical character recognition with considerable success. One such neural network is the neocognitron, a real-valued, multi-layered hierarchical network that simulates the human visual system. The neocognitron was shown to have the capability for pattern recognition despite variations in size, shape or the presence of deformations from the trained patterns. Unfortunately, the neocognitron is an analog network which prevents it from taking full advantage of the many advances in "VLSI technology. Major advances in VLSI technology have been in the digital medium. Therefore, it appears necessary to adapt the neocognitron to an efficient digital neural network if it is to be implemented in VLSI. Recent research has shown that through preprocessing approximations and definition of new model functions, the neocognitron is well suited for implementation in digital VLSI. This thesis uses this methodology to implement a large scale digital neocognitron model. The new model, the digi-neocognitron...

This thesis illustrates the design of a chip to crack a message encrypted with Digital Encryption Standard (DES). VHSIC Hardware Description Language (VHDL) is used to describe the system. Part of the design criteria of the system is to provide a scalable and reconfigurable set of DES building blocks in VHDL. In order to provide this, a modular design with a pipeline architecture is employed. This system could be synthesized to produce actual hardware in either an ASIC or FPGA part. Simulations using Synopsys with Actel's 3200DX FPGA library demonstrate that the design could be run at over 16Mhz. Because a pipelined architecture is employed which retires one key every clock cycle the chip would be able to test over 1 6 million keys per second. This is a vast improvement over current software-only based approaches that achieve speeds of 1 to 2 million keys per second on expensive high-end micro-processors.

Visual programming languages promise to make programming easier with simpler graphical methods, broadening access to computing by lessening the need for would-be users to become proficient with textual programming languages, with their somewhat arcane grammars and methods removed from the problem space of the user. However, after more than forty years of research in the field, visual methods remain in the margins of use and programming remains the bailiwick of people devoted to the endeavor. VPL designers need to understand the mechanisms of usability that pertain to complex systems like programming language environments. Effective research tools for studying usability, and sufficiently constrained, mature subjects for investigation are scarce. This study applies a usability research tool, with its origins in applied psychology, to a programming language surrogate from the hardware description language class of notations. The substitution is reasonable because of the great similarity between hardware description languages and programming languages. Considering VHDL (the VHSIC Hardware Description Language) is especially worthwhile for several reasons, but primarily because significant numbers of digital designers regularly employ both textual and visual VHDL environments to meet the same real-world design challenges. A comparative analysis of Cognitive Dimensions assessments of textual and visual VHDL environments should further understanding of the usability issues specifically related to visual methods – in many cases...

Very high speed integrated circuit Hardware Description Language (VHDL) is utilized in this project to model a Morphological Image Processor (MIP) Array. Both behavioral and structural models have been established at the system level, and the simulation results from both models are consistent with each other. The successful implementation of the models accomplishes our original goal to document the MIP with VHDL. It is observed from the project that VHDL is a powerful language. It is flexible since it can be used to model any level of a system independent of the technology.